1. Field of the Invention
The present invention relates to a fabricating method of a semiconductor device.
2. Description of the Related Art
A related art trench type metal-insulator-metal (MIM) capacitor is formed by fabricating method of semiconductor device illustrated in FIGS. 1A to 1C. FIGS. 1A to 1C are sectional views illustrating a related art method of forming a trench type metal-insulator-metal (MIM) capacitor.
Referring to FIG. 1A, an oxide layer 3 is formed on a predetermined substrate 1. Then, a metal layer is formed on the oxide layer 3 and is patterned to form a bottom metal line 5 and a bottom electrode 7 of a capacitor. The bottom metal line 5 and the bottom electrode 7 can be formed of aluminum (Al) having good conductivity.
Next, an interlayer insulating layer 9 is formed on the resulting structure, and a trench 10 is formed according to a capacitor structure. A dielectric layer 11 is then formed on the resulting structure.
Referring to FIG. 1B, a via hole 13 is formed. A contact 15 connecting to the bottom metal line 5 is formed by depositing tungsten (W) using a chemical vapor deposition (CVD) process.
Referring to FIG. 1C, all tungsten layer except the inside of the via hole 13 and the inside of the trench 10 is removed using a chemical mechanical polishing (CMP) process. An aluminum (Al) layer is deposited on the resulting structure and is patterned to form a top metal line 17 and a top electrode 19 of the capacitor.
Meanwhile, as the integration density of the semiconductor device is increasing, many attempts have been made to increase the capacitance of the capacitor using a dielectric layer with large dielectric constant. Silicon nitride (SiN) with a relatively large dielectric constant has been widely used as the dielectric layer of the MIM capacitor.
In summary, the related art fabricating method of the semiconductor device includes forming the trench according to the MIM capacitor structure, forming the silicon nitride (SiN) layer as the dielectric layer, and forming the via hole. However, such a related art fabricating method of the semiconductor device has the following problems.
First, an amine component of a deep ultraviolet (DUV) photoresist used in an exposure process when forming the via hole reacts with nitrogen of the silicon, nitride (SiN) layer, thus forming polymer. The polymer may remain on the surface of the silicon nitride (SiN) layer after the patterning process. Also, the polymer is difficult to remove. The polymer remaining on the surface of the silicon nitride (SiN) layer weakens the adhesion between tungsten and silicon nitride (SiN).
In addition, the tungsten (W) CVD has a high compressive characteristic. Therefore, when tungsten (W) is deposited in a relatively wide area, a tungsten (W) peeling phenomenon may occur. Since the trench region for the MIM capacitor has 100-1000 times the size of the via hole, it exists in a relatively wide area. A stress control of the tungsten is very important. However, it is very difficult to control the stress of the tungsten.
Further, if the trench is first formed and the via hole is then formed, a dishing phenomenon may occur in the trench region during the CMP process after the deposition of the tungsten. An over polishing may also occur. In the case of the trench region where tungsten with a high compressive characteristic is deposited, the tungsten may be peeled more easily during the CMP process.
As described above, when the polymer exists on the surface of the silicon nitride layer (SiN), the danger of the tungsten peeling phenomenon and the dishing phenomenon is increased. Consequently, defect occurs in the semiconductor device with the MIM capacitor, thus degrading the reliability of the semiconductor device.